1. Homework Statement My homework is to design a Serial Adder in Verilog using a shift register module, a full adder module, and a D Flip-Flop module. I know my full adder and flip flop modules are correct, but I am not so sure about my shift register. The shift register is 8 bits: Inputs for the shift register are: Si, CLK, Reset Outputs for the shift register are: So, D7 through D0 (one for each bit of the register) Also, if anyone can give me a hint as to how I can approach designing a test bench would be extremely helpful. 3. The Attempt at a Solution
Jump to Verilog code - parameter S_C = 2'd3. Parameter S_D = 2'd2. Reg [ 1: 0 ] state. Always @( posedge clk). Verilog code for an N-bit Serial Adder with Testbench code Normally an N-bit adder circuit is implemented using N parallel full adder circuits, simply connected next to each other. The advantage of this is that, the circuit is simple to design and purely combinatorial.